Module Instance Parameter Value Assignments

(While you didn't actually ask a question...)

 

The # syntax is for the definition and instantiation overriding of parameters.

 

In a module declaration, the things in the #( ...) are a place to define parameters. These are functionally the same as a parameter defined in the body of the module with the exception that the parameters defined here can also be used in the port list of the module. For example

 

module my_module #(  parameter WIDTH = 8 ) (

  input [WIDTH-1:0] my_input;

  output [WIDTH-1:0] my_output;

);

 

When this module is instantiated, the parameter WIDTH can be overridden at instantiation time. For example if I wanted to instantiate this module with the parameter WIDTH=16, which would therefore make my_input and my_output 16 bits wide, it would be done with

 

my_module #(.WIDTH(16)) my_module_i0 (

  .my_input (my_16bit_input),

  .my_output (my_16bit_output)

);

 

Avrum

Generally, the idea behind the (added to the Verilog-2001 standard) is to protect value of from accidental or incorrect redefinition by an end-user (unlike a value, this value can't be modified by parameter redefinition or by a statement).

Based on IEEE 1364-2005 (ch. 4.10.2):

Verilog HDL local parameters are identical to parameters except that they cannot directly be modified by defparam statements or module instance parameter value assignments. Local parameters can be assigned constant expressions containing parameters, which can be modified with defparam statements or module instance parameter value assignments.

Additionally, in SystemVerilog (IEEE 1800-2012 (ch. 6.20.4)):

Unlike nonlocal parameters, local parameters can be declared in a generate block, package, class body, or compilation-unit scope. In these contexts, the parameter keyword shall be a synonym for the localparam keyword.

Local parameters may be declared in a module’s parameter_port_list. Any parameter declaration appearing in such a list between a localparam keyword and the next parameter keyword (or the end of the list, if there is no next parameter keyword) shall be a local parameter. Any other parameter declaration in such a list shall be a nonlocal parameter that may be overridden.

If you want to learn more about this topic, I'd recommend you Clifford E. Cummings paper "New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)".

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